Google Scholar

Full publication list and citation metrics are available on my Google Scholar profile .

Selected Publications

Journals

  1. K. Park, H. Jeong, Yoontae Jung, J.-H. Suh, M. Je, and J. Kim, “Using biopotential and bio-impedance for intuitive human–robot interaction”, Nature Reviews Electrical Engineering, Jul. 2025.

  2. Y. Kim, C. Seok, Yoontae Jung, S.-J. Kweon, S. Ha, and M. Je, “A Montion-Artifact-Tolerant Biopotential-Recording IC with a Digital-Assisted Loop,” IEEE Transactions on Biomedical Circuits and Systems, Jan. 2025.

  3. D. Youn, Y. Kim, I. Choi, Yoontae Jung, H. Jeon, K. Lee, S.-J. Kweon, S. Ha, and M. Je, “A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC With Optimized CCO Frequency”, IEEE Access, Jul. 2024.

  4. Yoontae Jung, Sein Oh, S. Ha, and M. Je, “A 187-dB FoMS Power-Efficient Second-Order Highpass Delta-Sigma Capacitance-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Apr. 2024.

  5. J.-H. Suh, H. Choi, Yoontae Jung, S. Oh, H. Cho, N. Koo, S. J. Kim, C. Bae, S. Ha, and M. Je, “A 16-channel Impedance-Readout IC with Synchronous Sampling and Baseline Cancellation for Fast Neural Electrical Impedance Tomography”, IEEE Solid-State Circuits Letters, vol. 6, pp. 109–112, Apr. 2023.

  6. D. Cho, H. Cho, S. Oh, Yoontae Jung, S. Ha, C. Kim, and M. Je, “A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current”, IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 720–731, Mar. 2023.

  7. Yoontae Jung, S.-J. Kweon, H. Jeon, I. Choi, J. Koo, M. K. Kim, H. J. Lee, S. Ha, and M. Je, “A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom Delta-Sigma ADC for Saturation-Free Closed-Loop Neural Interfaces”, IEEE Journal of Solid-State Circuits, Oct. 2022.

  8. K. Jeong, Yoontae Jung, G. Yun, D. Youn, Y. Jo, H. J. Lee, S. Ha, and M. Je, “A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping SAR ADC With Chopper-Based Passive High-Pass IIR Filtering for Direct Neural Recording”, IEEE Transactions on Biomedical Circuits and Systems, Aug. 2022.

  9. Yoontae Jung, Soon-Jae Kweon, T. Lee, K. Jeong, S. Ha, and M. Je, “Dynamic-Range-Enhancement Techniques for Artifact-Tolerant Biopotential-Acquisition ICs”, IEEE Transactions on Circuits and Systems II, Jul. 2022.

  10. I. Choi, E. J. Choi, D. Yi, Yoontae Jung, H. Seong, H. Jeon, S.-J. Kweon, I.-J. Chang, S. Ha, and M. Je, “An SRAM-based Hybrid Computation-In-Memory Macro using Current-Reused Differential CCO”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 4, pp. 536–546, Jun. 2022.

  11. H. Shin, J. Kim, D. Jang, D. Cho, Yoontae Jung, H. Cho, U. Lee, C. Kim, S. Ha, and M. Je, “An Energy-Efficient Three-Stage Amplifier Achieving a High Unity-Gain Bandwidth for Large Capacitive Loads Without Using a Compensation Zero”, IEEE Solid-State Circuits Letters, vol. 3, pp. 530–533, Nov. 2020.

  12. S. Shin, Yoontae Jung, S.-J. Kweon, E. Lee, J.-H. Park, J. Kim, H.-J. Yoo, and M. Je, “Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy”, Sensors, vol. 20, no. 7, Mar. 2020.

  13. H. Jeon, J.-S. Bang, Yoontae Jung, I. Choi, and M. Je, “A High Dynamic Range, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface”, IEEE Journal of Solid-State Circuits, Oct. 2019.

Conferences

  1. X. Yang, Q. Lin, Yoontae Jung, A. Rivero-Cortazar, C. Sawigun, B. C. Raducanu, J. C. Fernandez, J. Aymerich, and C. M. Lopez, “Circuit Architectures for Next-Generation Neural Interfaces: Recording, Stimulation, and Closed-Loop Neuromodulation”, IEEE Custom Integrated Circuits Conference, 2026 (Accepted).

  2. J. Koo, S. Oh, Yoontae Jung, V. Lukito, S. Ha, and M. Je, “A 6 µW ECG-Recording Delta-Sigma Modulator with Internal-Capacitor-Flipping Technique for 34 Vpp Common-Mode-Interference Tolerance and 1 Vpp Input Range”, IEEE Custom Integrated Circuits Conference, 2025.

  3. G. Yoon, H. Choi, Yoontae Jung, J. Myung, S. Oh, S. Ha, and M. Je, “A 189.3 dB FoMS 14.5 fJ/Conversion-Step Continuous-Time Noise-Shaping SAR Capacitance-to-Digital Converter”, IEEE International Solid-State Circuits Conference, 2025.

  4. Woobean Lee, Yoontae Jung, H. Jeon, J. Koo, S. Oh, S.-J. Kweon, and M. Je, “An Area-Efficient, DC-Coupled VCO-Based Continuous-Time Delta-Sigma Modulator with Input TR-DAC for Neural Recording”, IEEE International Symposium on Circuits and Systems, 2024.

  5. J.-H. Suh, H. Choi, Yoontae Jung, S. Ha, and M. Je, “A 5.7 kfps Fast Neural Electrical Impedance Tomography IC Based on Incremental Zoom Structure with Baseline Cancellation for Peripheral Nerve Monitoring Systems”, IEEE Symposium on VLSI Circuits, 2024.

  6. Yoontae Jung, Sein Oh, J. Koo, S. Park, J.-H. Suh, D. Cho, S. Ha, and M. Je, “A 187 dB FoMS 46 fJ/Conversion 2nd-Order Highpass Delta-Sigma Capacitance-to-Digital Converter”, IEEE Symposium on VLSI Circuits, 2023.

  7. S. Oh, S. Park, Yoontae Jung, J. Koo, D. Cho, S. Ha, and M. Je, “A 2.5 mW 12 MHz Bandwidth 69 dB SNDR Passive Bandpass Delta-Sigma ADC with Highpass Noise-Shaping SAR Quantizers”, IEEE Symposium on VLSI Circuits, 2023.

  8. Yoontae Jung, S.-J. Kweon, H. Jeon, J. Lee, Y. Kim, S. Oh, J. Koo, and M. Je, “A Sub-attofarad Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass Delta-Sigma ADC”, IEEE International Symposium on Circuits and Systems, 2023.

  9. Yoontae Jung, J. Koo, S. Oh, S. Park, J.-H. Suh, D. Cho, and M. Je, “A 56 fJ/Conversion-Step 178 dB FoMS Third-Order Hybrid Continuous-Time Discrete-Time Delta-Sigma Capacitance-to-Digital Converter”, IEEE Custom Integrated Circuits Conference, 2023.

  10. J.-H. Suh, H. Choi, Yoontae Jung, S. Oh, H. Cho, N. Koo, S. J. Kim, C. Bae, S. Ha, and M. Je, “A Synchronous-Sampling Impedance-Readout IC with Baseline-Cancellation-Based Two-Step Conversion for Fast Neural Electrical Impedance Tomography”, IEEE Asian Solid-State Circuits Conference, 2022.

  11. D. Cho, H. Cho, S. Oh, Yoontae Jung, S. Ha, C. Kim, and M. Je, “A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58 Percent Efficiency at 1 Ampere in Boost Operation”, IEEE Custom Integrated Circuits Conference, 2022.

  12. Yoontae Jung, S.-J. Kweon, H. Jeon, T. Lee, I. Choi, K. Jeong, M. K. Kim, H. J. Lee, S. Ha, and M. Je, “A 99.5 dB Dynamic Range 5 kHz Bandwidth Closed-Loop Neural Recording IC based on Continuous-Time Dynamic-Zoom Delta-Sigma ADC with Automatic AFE Gain Control”, IEEE Asian Solid-State Circuits Conference, 2021.

Patents

  1. KR10-2021-0189924 (Granted): Impedance Measuring Apparatus and Impedance Measuring Method, Mar. 2024.

  2. KR10-2520512 (Granted): Band Pass Modulator Capable of Controlling Passing Frequency Band, Apr. 2023.

  3. KR10-2515176 (Granted): Adaptive Gain Control Neural Signal Detection Circuit, Mar. 2023.

  4. KR10-2023-0114327 (Filed): An Energy-Efficient Continuous-Time Discrete-Time Hybrid Delta-Sigma Capacitance-to-Digital Converter, Aug. 2023.

  5. KR10-2022-0147590 (Filed): A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping Successive Approximation Register Analog-to-Digital Converter for Direct Neural Recording, Dec. 2022.

  6. KR10-2022-0147589 (Filed): Wide-Input Range and Input Impedance Boosting Noise-Shaping Successive Approximation Register Nested Delta-Sigma Modulator for Bio-Signal Acquisition, Dec. 2022.